Left Shift Instruction

Shifting the accumulator one bit to the left can be easily accomplished by adding it to itself. To shift by a variable number of bits, however, we will need to have a loop in the microcode, which brings us to the subject of microcode branching.

Microcode Branching

To support branching in the microcode, I added two new control fields: UBCOND (Microcode Branch Condition) and UBADDR (Microcode Branch Address).

UBCOND selects one of a number of branch conditions. The branching logic is as follows:

When the branch condition is true, the next value for STATENO is taken from the UBADDR field.
When the branch condition is false and EOI is true, STATENO is reset to zero.
Otherwise, STATENO is incremented.

I made some additions to the State Counter subcircuit to implement this logic.

UBRANCH is a new input to the State Counter that is 1 when the selected branch condition is true. It is generated by a multiplexer in the main circuit:

Note that I changed how the LAST signal is generated again. It is now an output from the State Counter subcircuit, and is only activated if EOI is true and UBRANCH is false.

I have defined two UBCOND values so far:

UBCOND	Branch condition
000	Always false
001	Bit 0 of the S Register = 0

Left Shift Instruction

The number of places to shift is encoded in the Shift Left and Shift Right instructions by the position of the rightmost 1 bit in the instruction. This means we can take advantage of the fact that the instruction is left in the S Register at the end of the fetch cycle. Here's the strategy:

To do this, I added a control signal SS1 that shifts the S register only during T17. I used the bit that became spare when AND was removed.

Left Shift Microcode

The microcode for the Left Shift instruction takes 4 microinstructions, because it needs to shift all four short words of the accumulator. Shifting the S register is overlapped with both shifting the most significant accumulator short word, and with the branch back to the beginning if there is more shifting to be done. Note that the branch condition is testing the state of the S register before it is shifted.

# OPCODE L STAT : FETCH MASEL SHS EOI RFA WRF XSEL YSEL  CMX SS1 CY1 CYP ODD MSW LSW HALT WMEM UBCOND UBADDR

# L - Left shift
   11001 x 0001 :   0     0    0   0   00  10   10   10   0   0   0   0   0   0   1   0    0    000    0000
   11001 x 0010 :   0     0    0   0   10  10   10   10   0   0   0   0   0   0   0   0    0    000    0000
   11001 x 0011 :   0     0    0   0   01  10   10   10   0   0   0   0   0   0   0   0    0    000    0000
   11001 x 0100 :   0     0    0   1   11  10   10   10   0   1   0   0   0   1   0   0    0    100    1000